This invention relates generally to semiconductor memories and more particularly to the read circuitry of semiconductor memories.
As digital computer systems become faster and more powerful there is an increasing demand for faster semiconductor memories. While a number of factors contribute to the overall speed of semiconductor memories, efficiently dealing with bit line delay has been a continuing problem.
With reference to FIG. 1a, prior art semiconductor memories M typically include a number of memory cells C arranged in a two dimensional array or matrix. Rows of memory cells within the matrix correspond to words W of memory, while columns of memory cells correspond to bits B within the words of memory. The rows of memory cells are coupled to a row decoder D by word lines W.sub.1 and the columns of memory cells are coupled to a sense amplifier S a complementary pair of bit lines B.sub.1.
During a read cycle, a row address A.sub.r is applied to the row decoder D to cause a selected word line W.sub.1 to activate all of the memory cells C in that row. The memory cells develop an output on the bit lines B.sub.1 representative of their memory state. The signal level on the bit lines are typically very small, i.e. often on the order of 0-5 volts d.c. The sense amplifier S senses and amplifies the signals on one of the bit line pairs selected by a column address A.sub.c to produce an output bit O corresponding to the logical content of the memory cell at the selected row and column.
Since the signals on the bit lines have a finite rise and fall time, the sense amplifier must be told when it is time to sense the bit lines in order to ensure that valid data is being sensed. The sense amplifier S is controlled by a sense amplifier clock S.sub.c which activates the sense amplifier after the activation of a word line and after the selected bit lines are ready for sensing.
A prior art method for developing the clock S.sub.c involves the use of a dummy bit line B.sub.d. One end of the dummy bit line is coupled to V.sub.cc by a transistor T.sub.p and the other end of the bit line is coupled to sense amplifier control logic L.sub.s. The dummy bit line is also coupled to each of the word lines W.sub.1 by a transistor T.sub.w.
In operation, the dummy bit line B.sub.d is first precharged to V.sub.dd by turning on transistor T.sub.p with a precharge signal. When the dummy bit line is precharged, the sense amplifier control logic L.sub.s produces a clock S.sub.c level which deactivates the sense amplifier S. When any one of the word lines W.sub.1 is activated, the corresponding transistor T.sub.w is turned on and the dummy bit line B.sub.d is grounded through the transistor to cause the control logic L.sub.s to produce a clock S.sub.c level which activates the sense amplifier.
While the prior art dummy bit line method for dealing with bit line delay serves its purpose, it introduces an unnecessary delay into the read cycle, thereby increasing memory access times. This is primarily due to the fact that while the bit lines B.sub.1 only have to move 0.5 volts to be sensed, the dummy bit line B.sub.d has to move approximately 2.5 volts to trigger the sense amplifier control logic L.sub.s.
The nature of this problem can be clearly seen in the timing diagram of FIG. 1b. If a word line W.sub.1 is activated at a time t.sub.0, the bit lines may change in voltage an amount dv of approximately 0.5 volts d.c. after a first time delay of t.sub.d1. However, the dummy bit line B.sub.d has to drop to approximately 2.5 volts d.c. after a second time delay t.sub.d2 before the sense amplifier control logic L.sub.s can sense the change. The sense amplifier control logic has its own delay, creating a third time delay t.sub.d3 before the sense amplifier can be clocked. Since the bit lines were ready to sense after the time delay t.sub.d1 but are not actually sensed until time delay t.sub.d3, the dummy bit line method of the prior art creates an excess delay of t.sub.d3 -t.sub.d1 in every read cycle of the semiconductor memory.
What the prior art fails to disclose, then, is an effective method for dealing with bit line delay in semiconductor memories.